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Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

Home Page:http://veripool.org/verilog-mode

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SUMMARY

This is the source distribution repository for verilog-mode, the Verilog editing and AUTOs package which is part of GNU Emacs (lisp/progmodes/verilog-mode.el).

DOCUMENTATION

See https://www.veripool.org/verilog-mode for more information.

TESTS

The main purpose of this repository is the extended test suite. (Verilog-mode.el itself being both here and in the GNU Emacs repository.)

To run the tests, make sure both GNU Emacs and Xemacs are installed, then:

make
make test

Under the hood this is (mostly) running 0test.el. This reads in each file under tests/ directory, AUTOs, reindents, and compares the result to the matching filename in the tests_ok directory.

Test failures generally look like this:

diff -c tests_ok/autoinout_ma.v e/t/autoinout_ma.v
***Golden Reference File
---Generated Test File
--- GOLDEN_REFERENCE
+++ CURRENT_BEHAVIOR
...
-   output sina,
+   output siuna,
To promote current to golden, in shell buffer hit newline anywhere in next line (^P RETURN):
cp e/t/autoinout_ma.v tests_ok/autoinout_ma.v; VERILOG_MODE_START_FILE=tests_ok/autoinout_ma.v make test_emacs

This indicates the generated output doesn’t match what is in tests_ok. To fix this make sure that the change is expected then do the cp shown to update the golden references:

cp e/t/autoinout_ma.v tests_ok/autoinout_ma.v

Then make test again. The output also suggests a VERILOG_MODE_START_FILE which can also be used to jump right to that individual test inside the make test.

LICENSE

Verilog-mode itself is part of GNU Emacs, which is Copyright © 2001-2019 Free Software Foundation, Inc. This package is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License Version 3.

The Verilog test files unless specified otherwise are released into the public domain.

About

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

http://veripool.org/verilog-mode

License:GNU General Public License v3.0


Languages

Language:Verilog 51.9%Language:Emacs Lisp 41.9%Language:SystemVerilog 3.7%Language:Coq 0.8%Language:Perl 0.7%Language:V 0.7%Language:Makefile 0.4%Language:Forth 0.0%