binzheng305's repositories
32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
FPGA-1
数字IC相关资料
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Jacobi-EigenValue-And-EigenVectors
This repository is about finding the eigenvalues and eigenvectors of an image or any input matrix
Multiplier16X16
Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
NetworkSecuritySelf-study
这是作者的系列网络安全自学教程，主要是关于网安工具和实践操作的在线笔记，希望对大家有所帮助，学无止境，加油。
Paddle-Lite
Multi-platform high performance deep learning inference engine (『飞桨』多平台高性能深度学习预测引擎）
Python
最良心的 Python 教程：
SVD_CHIP
An ASIC designed under cell-based design flow. Developed by MATLAB for algorithm specification, by Verilog for RTL work, by Synopsys Design Compiler for logic synthesis, by Innovus for Place & Route, and taped out by CIC.
Verilog-FIR
FIR implemention with Verilog
VLSI
All the projects and assignments done as part of VLSI course.
VLSI_Practice
work done as part of VLSI Design practice course