benreynwar

pyvivado

Python tools for Vivado Projects

slvcodec

Generate conversions to/from VHDL types and std_logic_vector. Generate python-based tests.

htfft

A high throughput FFT implementation

axilent

Python to AXI4

fusesoc_generators

Add generators to fusesoc so that depenedencies can be generated from generic parameters.

202008_cocotb_presentation

verilate

Running python tests with verilator

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

aws-fpga-1

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

check_cocotb_ghdl

Just a check to make sure cocotb and ghdl are working together

cocotb

Coroutine Co-simulation Test Bench

cocotb-testrunner

Run tests with cocotb

CoSA

CoreIR Symbolic Analyzer

edalize

An abstraction library for interfacing EDA tools

fusesoc

FuseSoC is a package manager and a set of build tools for FPGA/ASIC development

ghdl

VHDL 2008/93/87 simulator

latte21

Languages, Tools, and Techniques for Accelerator Design

migen

A Python toolbox for building complex digital hardware

nmigen

A refreshed Python toolbox for building complex digital hardware

rust_hdl

symbiflow-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

SiLemma

Trying to prove things about circuits in Dafny

asyncio_workshop

cocotb-test

Unit testing for cocotb

dafny_experiments

Experiments while learning dafny

misc_dump

Miscellaneous stuff is getting dumped here.

openpiton

The OpenPiton Platform

silveroak

Formal specification and verification of hardware, especially for security and privacy.

verilog-axi

Verilog AXI components for FPGA implementation