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benishor / fpga-radio

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Language:VHDL 79.9%Language:Verilog 15.9%Language:SystemVerilog 1.8%Language:Tcl 0.9%Language:Shell 0.8%Language:JavaScript 0.5%Language:C 0.2%Language:Stata 0.1%Language:C++ 0.1%Language:Batchfile 0.0%Language:Pascal 0.0%Language:PureBasic 0.0%