Two synchronous 8-bit comparators for signed two's complement notation written structurally in VHDL, including individual gate time delay simulation. The first uses a ripple adder, while the second uses magnitude comparators. The second component achieves a functional frequency of 7 MHz.
| Gate | Delay |
|---|---|
| Inverter | 2 ns |
| NAND | 5 ns |
| NOR | 5 ns |
| AND | 7 ns |
| OR | 7 ns |
| XNOR | 9 ns |
| XOR | 12 ns |