asicguy

Minimig-AGA_MiSTer

verilog-ethernet

Verilog Ethernet components for FPGA implementation

xceed_se-306_48

HDL for xceed clone board

alice5

SPIR-V fragment shader GPU core based on RISC-V

ao486_MiSTer

ao486 port for MiSTer

Apple-II_MiSTer

Apple II+ for MiSTer

arcade-foodfight

FPGA foodfight arcade game in verilog

Atari7800_MiSTer

Atari 7800 for MiSTer

coco3_MiSTer

Coco3 port to Mister

Custom_Part_Data_Files

Xilinx PCIe to MIG DDR4 example designs and custom part data files

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

fx68k

FX68K 68000 cycle accurate SystemVerilog core

GBA_MiSTer

GBA for MiSTer

HT1080Z_MiSTer

port of HT1080Z to MiSTer (Tandy TRS-80 Model I)

MacPlus_MiSTer

Macintosh Plus for MiSTer

macsehw

Macintosh SE Hardware Designs

polyphony

3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.

Projects

vortex

BBCMicro_MiSTer

BBC Micro B and Master 128K for MiSTer

biriscv

32-bit Superscalar RISC-V CPU

croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

MiSTeX-boards

Core generation scripts for various FPGA boards

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

openc910

OpenXuantie - OpenC910 Core

RISCV-FiveStage

Marginally better than redstone

Vitis_Hero

wolv-z7

Wolv Z7 is a RISC-V CPU core with floating point unit

yrv-sv

Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.