asamarah1 / pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog

pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog.

Generates PCIe Physical, Data Link and Transaction Layer traffic for up to 16 lanes, controlled from user C program, via an API. Has configurable internal memory and configuration space models, and will auto-generate completions (configurably), with flow control, ACKs, and NAKS etc.

pcievhost is bundled with verilog pcie link traffic display modules and an example test harness. Tested for ModelSim/Questa only at the present time, though easily adpated for VCS, NC-Verilog and Icarus (and has previously been running on these in the past).

More informaton can be found in the documentation doc/pcieVHost.pdf