Arpit Sharma's repositories
5-Stage-Pipelined-MIPS32-RISC-Processor-Design-on-Verilog
This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined configuration.
4-Bit-LFSR-IC-design-and-analysis
This repository presents the IC design of a 4-Bit Linear Feedback Shift Register (LFSR) also known as Pseudo Random Binary Sequence Generator; on 90nm CMOS technology.
Implementation-of-CMOS-Schmitt-Trigger
This repository presents the design of Schmitt Trigger implemented using Synopsys Custom Compiler tool on 28nm CMOS Technology.
Design-of-Toffoli-Quantum-Gate
This circuit simulation project presents the design and simulation of Toffoli Gate using open-source tool eSim and Sky130 PDK library; done under the FOSSEE 2022 circuit simulation project.
eSim
In this repository I have added added my contributions during FOSSEE eSim Fellowship 2022.
VSD-IAT-Sign-off-Timing-Analysis-Basics-to-Advanced
In this workshop we studied the concepts involved in STA from basics to advanced, with the help of open source STA tools and libraries.