annosoo's starred repositories
ccf-deadlines
⏰ Collaboratively track deadlines of conferences recommended by CCF (Website, Python Cli, Wechat Applet) / If you find it useful, please star this project, thanks~
BinaryNet.pytorch
Binarized Neural Network (BNN) for pytorch
XNOR-Net-PyTorch
PyTorch Implementation of XNOR-Net
Neuromorphic-Computing-Guide
Learn about the Neumorphic engineering process of creating large-scale integration (VLSI) systems containing electronic analog circuits to mimic neuro-biological architectures.
ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
open-neuromorphic
List of open source neuromorphic projects: SNN training frameworks, DVS handling routines and so on.
awesome-neuromorphic-hw
Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.
Transformer-Accelerator-Based-on-FPGA
You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.
universal_NPU-CNN_accelerator
hardware design of universal NPU(CNN accelerator) for various convolution neural network
DNN-Accelerator
A DNN Accelerator implemented with RTL.
CNNAF-CNN-Accelerator_init
CNN-Accelerator based on FPGA developed by verilog HDL.
CyNAPSEv11
The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL
CNN-ACCELERATOR
Hardware accelerator for convolutional neural networks
awesome-approximate-dnn
Curated content for DNN approximation, acceleration ... with a focus on hardware accelerator and deployment
CNN-hw-accelerator
CNN hardware accelerator to accelerate quantized LeNet-5 model
QuantizedSNNs
This repository contains the models and training scripts used in the papers: "Quantizing Spiking Neural Networks with Integers" (ICONS 2020) and "Memory Organization for Energy-Efficient Learning and Inference in Digital Neuromorphic Accelerators" (ISCAS 2020).
Chisel3-Float-Type
Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)
FusionAccel
RTL-level Convolutional Network Accelerator Implementation on Xilinx Spartan 6. Evaluation for scalability.
izhikevich-graph-accelerator
Verilog specification for a programmable izhikevich spiking neural network accelerator
ECE-564-Convolutional-Neural-Network-Accelerator
A Verilog implementation of a CNN accelerator.
GP_DRAM_Hardware_accelerator
plug and play verilog FSMs for and array of algorithms
DQN-Accelerator
This project consists of RTL codes which are designed using Verilog HDL.