Andrew Butt's repositories
Language:JavaScriptMIT000
bril
an educational compiler intermediate representation
Language:RustMIT000
calyx
Intermediate Language (IL) for Hardware Accelerator Generators
Language:RustMIT000
Language:SystemVerilog000
Language:Rust000
Language:C++000
Language:Java000
cs6120
advanced compilers
Language:HTMLMIT000
Language:Rust000
dahlia
Time-sensitive affine types for predictable hardware generation
Language:ScalaMIT000
fasm
FPGA Assembly (FASM) Parser and Generator
ISC000
litedram
Small footprint and configurable DRAM core
Language:PythonNOASSERTION000
litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
BSD-2-Clause000
OpenSTA
OpenSTA engine
Language:C++GPL-3.0000
prjxray
Documenting the Xilinx 7-series bit-stream format.
Language:PythonISC000
Language:Verilog000
Language:Python000
symbiflow-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Language:Jupyter NotebookISC000
Language:VerilogMIT000
symbiflow-examples
Example designs showing different ways to use SymbiFlow toolchains.
Language:VerilogISC000
vast
Verilog AST
Language:RustApache-2.0000
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language:C++NOASSERTION000