Part of Advanced Computer Architecture Lab 3. Simulated Tomasulo’s Algorithm. Simulated a 7 stage pipeline, Register Alias Table (RAT), ReOrder Buffer (ROB). Specifically implemented Issue, Schedule, Writeback and Commit Stages. This design is evaluated against SPEC traces.
How to Run?
- cd folder-name
- cd src
- make
- ./sim –h (to see the simulator options)
- ../scripts/runall.sh runs all configurations for all traces