xalamin's repositories
Xilinx-Vitis-AI
The Flow to Deploy your Custom Deep Learning Models on Ultra96V2.
Operating-Systems
Lab Assignments and Projects for OS - EECS678
amin-mamandi.github.io
Personal Website
aws-fpga
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
blog
Build a Jekyll blog in minutes, without touching the command line.
cloudWorkloads
Scripts for running cloudSuite workloads
computer-architecture-and-systems-resources
A curated list of Computer Architecture and Systems resources
CXLMemSim
A place to store the CXL simulator
ddio-bench
Reexamining Direct Cache Access to Optimize I/O Intensive Applications for Multi-hundred-gigabit Networks
fluidmem
Open memory disaggregation
FPGA_Design_Fabric_Architecture
This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primarily focused on a complete FPGA flow using the maximum open-source tools.
gem5-CXL
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
gem5-fullsys-environment
A baseline environment for simple gem5 development. Everything you need to use full system mode is already built, the possibilities of new developments are yours!
gem5.TnT
gem5 Tips & Tricks
linux-kernel-module-cheat
The perfect emulation setup to study and develop the Linux kernel v5.4.3, kernel modules, QEMU, gem5 and x86_64, ARMv7 and ARMv8 userland and baremetal assembly, ANSI C, C++ and POSIX. GDB step debug and KGDB just work. Powered by Buildroot and crosstool-NG. Highly automated. Thoroughly documented. Automated tests. "Tested" in an Ubuntu 20.04 host.
microrev
Reverse Engineering Micro-architectural Features
PIMSimulator
Processing-In-Memory (PIM) Simulator
research-course
"How to Do Great Research" Course for Ph.D. Students
siliconCompiler
A modular build system for hardware
VeriGPU
OpenSource GPU, in Verilog, loosely based on RISC-V ISA