alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Bug in udp_checksum_gen

SebastianSchelle opened this issue · comments

I am streaming out small packets (about 50 to 60 bytes payload). When hitting the bandwidth limit, in this case 100M, the FIFOs start to fill up and afterwards old payload data is still stuck in the payload FIFO. Thus, when trying to send out new data, stale data is sent to the PHY.

Analysis with the ILA showed, that this happens when the header FIFO inside the udp_checksum_gen is full. The following screencap shows that with a full FIFO, some headers are just dropped (FIFO full, header is not written) even though the logic waits for assertion of hdr_ready. Then, payload and header FIFO are drifting apart as payload is still accepted.
lost_header_udp_checksum_gen

A simple fix on my side is to extend the state machine inside udp_checksum_gen to wait until the FIFO is ready again after STATE_FINISH_SUM before continuing to STATE_IDLE.
wait_for_ready_udp_checksum_gen