Unreachable code in ip_eth_tx_64.v

[MKCompu]

Hi, first I would like to say that I really like this project.
While browsing through the code in rtl/ip_eth_tx_64.v, I've noticed that the following code cannot be reached:

verilog-ethernet/rtl/ip_eth_tx_64.v

Lines 610 to 615 in baac5f8

 end else if (m_eth_payload_axis_tready) begin 
     // input is not ready, but output is ready 
     m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg; 
     temp_m_eth_payload_axis_tvalid_next = 1'b0; 
     store_eth_payload_axis_temp_to_output = 1'b1; 
 end 

The reason is, that m_eth_payload_axis_tready_int_early will get the value 1 if m_eth_payload_axis_tready is 1.
However, the first if case will always be taken if this is the case, end therefore the last else if statement is never taken.

Is it correct that this is not working as intended? If so, how should the code behave?

[MKCompu]

Sorry, misread code. I see how it works now.