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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

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Can this design be validated on Alveo u50 card ?

lizajoseph opened this issue · comments

commented

Hi,

I came across your design as I am looking for a Ethernet design with UDP listener to be implemented on FPGA. I have a Alveo u50 card installed in my machine. I was able to generate the bitstream of your design. How can I validate this design on the Alveo u50 card? I can see that there is a simulation testbench environment available using cocotb. But I want to validate the design on my target platform. Is there any test environment that is available to test on hardware?

Liza

commented

Just load it via JTAG. For the U50, you'll need the special U50-specific JTAG adapter, I think the part number is HW-DMB-1-G.

commented

Yes, I have a programming cable that is attached to the u50 card. I can program the FPGA card using this programming cable. But could you let me know how I can test the FPGA logic directly on u50 card.

commented

I would like to test and validate the FPGA logic on the u50 card

commented

Right, once it's on the card, the example design will echo back UDP packets sent to it via the QSFP28 port. The readme has a couple of basic tests, you can use netcat, hping, arping, the udp_test.py script, etc.

commented

I have programmed the bitfile on the Alveo u50 card via the u50 programming cable. Then I tried to set the IP address for my u50 card using this command arp -s , however even though the card with new IP is detected when I ping there is no response. Then I tried to test the u50 card using the udp_test.py but 0 packets are received. Is there any step that I am missing here? Should I add a 10G NIC card and connect it to the Alveo u50 card?

0_UDP_packets

commented

Hi Alex,

Thanks for sharing the Readme and the IP address details that is configured on the FPGA card.
After programming the bitfile to the u50 card. I tried the netcat command with a text "hello" and then it is stuck, Similarly I see the same behavior with the hping command. How should I proceed further to debug this issue of not receiving the packets echoed back from the FPGA? Sharing the commands lines below for your reference.

(base) liza.joseph@fepc20:~/verilog-ethernet$ netcat -u 192.168.1.128 1234
hello

(base) liza.joseph@fepc20:~/verilog-ethernet$ sudo hping3 192.168.1.128 -2 -p 1234 -d 10
[sudo] password for liza.joseph:
HPING 192.168.1.128 (eno1 192.168.1.128): udp mode set, 28 headers + 10 data bytes

I also observe that the 10G NIC card which is connected to the u50 card is not getting detected after programming the fpga.bit, whereas when I program 10G ethernet example design bitfile the 10G NIC card is getting detected. Could you help me with the debug for this issue?

commented

if the link partner NIC is not detecting a link, then it sounds like something is wrong with the FPGA config that's being loaded on the U50. Which design specifically did you build, and specifically what are you using as a link partner? (For example, the 25G version "fpga" will not link-up at 10G, you'll need to build the design in the "fpga_10g" folder as that configures the transceivers for 10G). But you also say that the 10G ethernet example design results in a link up - what is this design? Is this a Xilinx example design?

commented

Yes, you are right. I had built the fpga_AU50 which you pointed out that it is 25G version. Now I have built the fpga_AU50_10g folder design and programmed the bitfile on the u50 FPGA card and now the UDP packets are getting echoed back from the FPGA. Thanks for all your help.

Note:
The 10G Ethernet IP example design I used to test the 10G NIC card link status is from below link
https://docs.xilinx.com/r/en-US/Vitis-Tutorials-Hardware-Acceleration/Using-GT-Kernels-and-Ethernet-IPs-on-Alveo