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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

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Misalignment/Deadlock in udp_checksum_gen_64.v

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Issue on udp_checksum_gen_64.v control flow.
With very small UDP payload, 32 bytes I'm working on right now, udp_checksum_gen can sometime consume more hdr than payloads.
When this happens, wrong checksum are seen on wireshark. Deadlock will occur in udp_ip_tx_64.v if I suddenly change payload size to something like 500 bytes.
On simulation, I notice that the state machine can launch twice when there are only one empty slot in hdr fifo. The full signal lags one cycle behind idle state decision, simulation shows adding a delaying state between STATE_FINISH_SUM_2 and STATE_IDLE seems to fix the issue.