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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

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PHY MAC latency

infamalex opened this issue · comments

commented

I'm working on a project that will be intercepting and modifying TCP traffic as it crosses between the two ports on the Alveo U50DD. Now the functionality is working, I am looking to measure and optimize the latency. I have found the latency to be around 550ns across the whole fpga design. When I remove all the logic and just connect both eth_mac_10g_fifo's together I still get around 270-300ns. This seems a lot higher than I expected it to be and I'm wondering if there's anything I can do to improve it.

commented

Not easily. I'm planning on doing some significant reworking to the PHY interface, not so much to support low latency but to support synchronous operation that's needed for things like white rabbit. This will use the synchronous gearboxes in the transceivers instead of the async gearboxes, which should also significantly improve latency. But doing this is going to involve overhauls of several different components, so it's probably not going to happen for a few more months.