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alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

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Question - Verilog-Ethernet vs 1G/2.5G Ethernet Subsystem

Beauxrel opened this issue · comments

commented

I was wondering if this project could be used as a replacement for the Ethernet subsystem provided by Xilinx in Vivado. The Subsystem holds a MAC, Ethernet Buffer and PCS/PMA module. The MAC is not free (~$600), so I am looking for alternate ways to get the same functionality.

Thanks!

commented

Best option at the moment is to use the MAC from this repo in combination with the (free-of-charge) Xilinx 1G PCS/PMA core. See the VCU108 or VCU118 example designs for how to wire this up. Eventually I'll probably have a 1G PCS/PMA in this repo as well, but I don't have a timeline for that at the moment.

commented

I'll give it a try and drop my results here.