How can we use verilog ethernet on zcu102?

[ahmet serdar]

Hi alex,
I want to use your verilog project. I have edited your fpga.v and fpga_core.v files to use on my petalinux project. When i debug tx_tready signal by using ila, it gives zero. What is the reason? I added just this parameters:
`
//udp params

input wire [47:0] local_mac_user,
input wire [31:0] local_ip_user,
input wire [31:0] server_ip_user,
input wire [31:0] gateway_ip_user,
input wire [31:0] subnet_mask_user,
input wire [15:0] udp_port_user,
input wire [15:0] udp_length_user, // 1032
input wire        udp_hdr_valid_user,
output wire [63:0]  rx_fifo_udp_payload_axis_tdata,
output wire [7:0]   rx_fifo_udp_payload_axis_tkeep,
output wire         rx_fifo_udp_payload_axis_tvalid,
input wire          rx_fifo_udp_payload_axis_tready,
output wire         rx_fifo_udp_payload_axis_tlast,
output wire         rx_fifo_udp_payload_axis_tuser,
input wire [63:0]  tx_fifo_udp_payload_axis_tdata,
input wire [7:0]   tx_fifo_udp_payload_axis_tkeep,
input wire         tx_fifo_udp_payload_axis_tvalid,
output wire        tx_fifo_udp_payload_axis_tready,
input wire         tx_fifo_udp_payload_axis_tlast,
input wire         tx_fifo_udp_payload_axis_tuser

`
What do you think about this problem?