alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Detect cable plug unplug status

lk-davidegironi opened this issue · comments

Hello Alex,

I'm using your library on a Xilinx Zynq (PL side) with a dual gigabit PHY. I use this both for UDP and RAW packets. No problem whatsoever.

I'm wondering if there's a way to detect the plug status, i mean if ethernet cable is connected or disconnected.

I ask you this cause if I disconnect ethernet cable after the FPGA startup stage, ethernet stop working. So my plan is to drive a reset signal to my ethernet module, which use your ethernet ip, to reset the module and make ethernet bus work again. Or there's another way you already implemented?

Thank you!