How to set DATA_WIDTH=32bit
myqlee opened this issue · comments
Hi @alexforencich ,
First of all, thank you for sharing this wonderful library.
I want to implement this project on Alveo U200 card. I follow verilog-ethernet/example/AU200/fpga_10g/README.md,
run make to build, but the DATA_WIDTH of the built project is 64bit, what I want is DATA_WIDTH=32bit. what should I do?
I’m eager to receive your kind feedback.
Thank you,
Eduardo
Unfortunately, this is not currently supported. The modules in this repo have not been fully parametrized, so for most modules there are separate 8 bit and 64 bit versions, and as a result the full stack currently only supports operation for 8 bits or for 64 bits. I have rewritten a few modules to support a parametrized data width so the same module can be used from 8 bits to 512 bits, but there is still a lot of work remaining to complete this process, and it is currently a low priority.
Thanks for the quick reply.
Here's the thing: I now have an IP core of PCS+PMA, and then implement MAC, that is, synthesis to implement an Ethernet.
I use the eth_mac_10g_fifo module (DATA_WIDTH=64bit) in your project, and write a 64bit to 32bit module by myself (to convert the 64bit axis to the 32bit axis), is it feasible?
The 10G MAC + FIFO includes both width conversion and clock domain crossing, so you can specify whatever width you like on the streaming interface and run it at whatever clock frequency you need, although be aware about bit rate and packet rate bottlenecks. The MAC itself only supports 32 bit or 64 bit XGMII. However, my PHY logic currently only supports 64 bits, so if you want to run the MAC in 32 bit XGMII mode, you'll need to use the Xilinx PCS/PMA core.
So I'm going to use the Xilinx PCS/PMA IP core(DATA_WIDTH=32bit), plus your eth_mac_10g_fifo module(DATA_WIDTH=32bit).
Thank you again!
Well, I have a few more details to ask you:
Q1: Lines 307 and 323 in axis_xgmii_tx_32.v:
xgmii_txd_next = {{3{ETH_PRE}}, XGMII_START}; // line 307
xgmii_txd_next = {ETH_SFD, {3{ETH_PRE}}}; // line 323
7 bytes of synchronous preamble and one byte of SFD, but the codes seem to have only 6 bytes of preamble and one byte of SFD. Why?
Q2: There are i2c_scl/i2c_sda and uart_rxd/uart_txd in fpga.v,
What are the i2c interface and uart interface used for?
If I only use the eth_mac_10g_fifo module, do I need to use the i2c interface and uart interface?
Q1: the XGMII start control character is sent in place of the first preamble byte. So it is 7 bytes of preamble.
Q2: they are not used, in many of the example designs there are a few other things connected that are not strictly necessary. I think those pins on the top-level are simply tied off.
Thank you very much!
Another question:
Q3: when I run "python3 test_ axis_ xgmii_ tx_ 64.py", it's OK. But when I run "python3 test_ axis_ xgmii_ tx_ 32.py", it would report an error as follows:
Q4: I use the two Xilinx PCS/PMA IP core(DATA_WIDTH=32bit): one for RX and another for TX.
So how many eth_mac_10g_fifo(DATA_WIDTH=32bit) modules do I use? One or two?