Subject ministred by Jader Alves de Lima Neto Task performed by Alexandre Genthner
Below can be seen the active schematics and its necessary signals for read (left) and write operation (right). It's also provided with a spectated signal output for the bitlines as well as for the charges voltages on the inverters terminals.
Simple SRAM layout with 6 transistors acting as memory cell.
Differently from the DRAM, I used a current-sensor since it's desirable to have a 'OUTPUT' signal.
Once defined and designed my SRAM project, the coerent signals stiulation proved to be troublesome. Those were obtain through the source on the image bellow, each with a specific '.txt' acting as a table for changes in voltage in accordance with time progression.
Separately was design the write driver, which can be seen bellow.
Bellow is the components derived from above topologies and structured as a top-level schematic.
As can be seen, once all signals were correctly inputed on the project, write and read operations were enable, defining the sucess and end of the task.
