aleemrehaman's starred repositories
AXI-Ethernet-UVM
A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
DDR3-controller-verification
DDR3 function verification environment in UVM
SPI-Interface
UVM Testbench to verify serial transmission of data between SPI master and slave
ethernet_10ge_mac_SV_UVM_tb
SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
AES-Processor
AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.
ECC-Encryption-System
This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
SystemVerilog-Implementation-of-DDR3-Controller
The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.
rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
DDR4MemoryController
HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
2-way-Set-Associative-Cache-Controller
Synthesizable and Parameterized Cache Controller in Verilog
Introduction-to-Computer-Architecture-Education-Kit
Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm processors
Subarashii-CPU
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
learn-fpga-amaranth
Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
SystemVerilogReference
training labs and examples
UVM-Examples
UVM examples and projects
riscv-ocelot
Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
I2SRV32-S-v1
Reconfigurable Computing Lab, DESE, Indian Institiute of Science