Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further analysis can be performed on the simulation data. The entire VCD file can be stored in a Python data structure and manipulated using standard hash and array operations. More details in the module file : Verilog_VCD.py . Originally written in Perl by Gene Sullivan (gsullivan@cpan.org) . Translated into Python by Sameer Gauria (sgauria+python@gmail.com) . Patches submitted by Scott Chin, Sylvain Guilley, Bogdan Tabacaru, Andrew Becker, and a substantial performance improvement by Matthew Clapp.