Akash K.'s repositories
rake
compiling DSLs to high-level hardware instructions
ramulator-pim
A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures
FaCT
Flexible and Constant Time Programming Language
hmc-intrinsics
Intrinsics are high level functions implemented in C language and are based in some ISAs. The mainly purpose is simulate these architectures in SiNUCA (Simulator of Non-Uniforme Caches)..
asl-interpreter
Example implementation of Arm's Architecture Specification Language (ASL)
gpu-rodinia
Rodinia benchmark
sccl
Synthesizer for optimal collective communication algorithms
MLP_NeuroSim_V3.0
Benchmark framework of synaptic device technologies for a simple neural network
rosette
The Rosette solver-aided host language, sample solver-aided DSLs, and demos
diospyros
Search-based compiler for high-performance DSP programming
3D_NeuroSim_V1.0
Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
Calculator
Calculator implemented in Java
CompilerJobs
A listing of compiler, language and runtime teams for people looking for jobs in this area
DNN_NeuroSim_V1.2
Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
tiramisu
A polyhedral compiler for expressing fast and portable data parallel algorithms
mini-era
Mini-ERA is a simplified still-representative version of the main ERA workload.
code-samples
Source code examples from the Parallel Forall Blog
asplos-2020-28-ae
Artifact Evaluation for #28
DRAMSim2
DRAMSim2: A cycle accurate DRAM simulator
nn_dataflow
Explore the energy-efficient dataflow scheduling for neural networks.
MPU-ASPLOS-2021
Source code of MPU simulator and compiler for ASPLOS 2021 submission.
validating-binary-decompilation
Scalable Validator for Binary Lifters
learning-K
K Learning Experience
X86-64-semantics
Semantics of x86-64 in K
sw
NVDLA SW