akilm

Akil M's repositories

Physical-Design

Physical Design Flow from RTL to GDS using Opensource tools.

MIT75 40

Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Square Root Operations based on the IEEE-754 standard for floating point numbers

Language:VerilogMIT38 40

MYTH-RV32I-core-akilm

RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

Language:CMIT7 30

Logic-Gates-Sizing-Automation

Determining the sizing of transistors using heuristic algorithms and logical effort to obtain optimal delay and power

Language:MATLABMIT3 20

Controller-Design-for-Wind-driven-DC-Generator

Language:Python1 10

Physical-Design-Openlane-Flow

RTL to GDS flow using Openlane tool flow.

MIT1 20

vsdstdcelldesign

This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedures on how to create a custom LEF file and plugging it into an openlane flow.

Language:VerilogApache-2.01 10