akhilhadli1

akhilhadli1

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PruningNeuralNetworks

This repository provides the implementation of the method proposed in our paper "Pruning Deep Neural Networks using Partial Least Squares"

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spi

SPI Master Core clone from OpenCores

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generic_fifos

generic_fifos from OpenCores/ASICS.ws

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tbgen

Generate testbench for your verilog module.

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FFT_ChipDesign

A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.

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32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

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AMBA-APB-Slave-Memory-Block

RTL Implementation of AMBA APB Protocol

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RISCV_Formal_Verification

Formal Verification of RISC V IM Processor

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SoC-Implementation-of-OpenMSP430-Microcontroller

The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 microcontroller family. Due to its characteristics, the openMSP430 was selected to integrate the System on Chip (SOC). This open-core, that will be implemented as an Application Specific Integrated Circuit (ASIC), was previously synthesized, for a SAEDCMOS 90nm target technology process.

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bM3tal

Metal 3DPrinter/CNC/PCB Milling Machine

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CNN_ON_FPGA

implement convolution neural network on FPGA based on VHDL design

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CNN-Based-FPGA

CNN implementation based FPGA

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zedboard_cnn

Vivado project of hardware Implementation of CNN on Xilinx Zedboard.

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