aj-stein-nist / tt_stopwatch_project_fpga

This is the FPGA testbed variant for the TinyTapeout design in the tt_stopwatch_project repo

Tiny Tapeout Verilog/TL-Verilog Project Template for FPGA Demo Board

Overview

This project provides a template for generating an FPGA bitstream for the TT03 Demo Board for a Verilog or TL-Verilog based design for Tiny Tapeout.

Project

A project derived from this template would be documented here.

What is Tiny Tapeout?

TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Verilog Project Setup

1. Add your Verilog files to the src folder.
2. Edit the info.yaml and update information about your project, paying special attention to the source_files and top_module properties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool.
3. Edit docs/info.md and add a description of your project.
4. Optionally, add a testbench to the test folder. See test/README.md for more information.

The GitHub action will automatically build the ASIC files using OpenLane.

Makerchip and/or TL-Verilog Projects

Makerchip is an online IDE for digital circuit design supporting Verilog or TL-Verilog projects. This starting template provides a virtual environment for Tiny Tapeout simulations.

• starting template (Ctrl-click for new tab)
• calculator circuit example (Ctrl-click for new tab)

This environment has been used in the course "ChipCraft: The Art of Chip Design". Course materials and student projects can be found in the course repo.

Makerchip/TL-Verilog Project Setup

To use Makerchip and TL-Verilog for your project:

1. Create your top-level Makerchip-compatible .tlv (TL-Verilog or Verilog) source file as a copy of this https://raw.githubusercontent.com/stevehoover/tt06-verilog-template/main/src/tt_um_template.tlv file.
2. In this new file, specify your module name as tt_um_<github-username>_<project-name> using the settings at the top of the file.
3. As you would for Verilog projects (above), edit info.yaml, docs/info.md, src/Makefile, and tb.v. For .tlv sources, these would reference the generated .v files, not the .tlv source.
4. Add the generated src/*.v to .gitignore to avoid committing it/them.

Note

In case of local build errors, note that the Makefile uses the cocotb Makefile which messes with the Python environment and can break the SandPiper(TM) command that compiles the .tlv code. If you encounter Python environment errors, look for the SandPiper command in the make output, and run it manually. Then run make (as a pre-check for testing via GitHub).

Enable GitHub actions to build the results page

• Enabling GitHub Pages

Resources

• FAQ
• Digital design lessons
• Learn how semiconductors work
• Join the community
• Build your design locally

What next?

• Review/complete your project documentation that explains your design, how it works, and how to test it.
• Submit your design to the next shuttle.
• Share your project on your social network of choice:
  • LinkedIn #tinytapeout @TinyTapeout
  • Mastodon #tinytapeout @matthewvenn
  • X (formerly Twitter) #tinytapeout @matthewvenn