agra-uni-bremen / riscv-freertos

FreeRTOS port for the RISC-V Virtual Prototype

FreeRTOS for RISC-V Virtual Prototype (VP)

This is a port of FreeRTOS to RISC-V with a focus of running it on the RISC-V VP (see https://github.com/vherdt/riscv-vp). This port is based on a fork from https://github.com/illustris/FreeRTOS-RISCV. To build the demo applications the RISC-V GNU toolchain is required. Build instructions for the toolchain are also available at https://github.com/vherdt/riscv-vp.

Contributors

The original port to priv spec 1.7 was contributed by Technolution

Update to priv spec 1.9: illustris

Update to priv spec 1.9.1: Abhinaya Agrawal

Bug fixes: Julio Gago

Update to priv spec 1.10: sherrbc1

Update to support external interrupt sources and demo applications for the RISC-V VP: vherdt

Build

You can edit main() in main.c (Demo/standard-demo/main.c, also check the other demos) to add your FreeRTOS task definitions and set up the scheduler.

To build a FreeRTOS demo (requires the RISC-V GNU toolchain to be available in PATH),

cd Demo/integrated-interrupts
make

Run

riscv-vp riscv-main.elf --memory-start=2147483648 --intercept-syscalls