This Project has been done under prof. Joycee Makie @ IIT Gandhinagar. The project contains tools to generate codes and implementation of arithmetic operations on a FPGA.
Repository from Github https://github.comadityatripathiiit/Python-Based-Automated-Verilog-Code-Generator-For-Arithmetic-UnitRepository from Github https://github.comadityatripathiiit/Python-Based-Automated-Verilog-Code-Generator-For-Arithmetic-Unit
