abunimeh

cmos_linux

151_Project

Project for 251/151

abunimeh.github.io

parking page

asic-rtl-lib

RTL cores and verification suites

axi

AXI4 and AXI4-Lite interface definitions and testbench utilities

AxiCores

AXI4-Compatible Verilog Cores, along with some helper modules.

common-hdl

D5MWEB

D5MWEB

davos

Distributed Accelerator OS

ece5745-tut5-asic-tools

ECE 5745 Tutorial 5: Synopsys ASIC Tools

ee241b_project

Build scripts and sources for the data gathering phase of the EE241B power estimation project.

fpga-family

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

freedom

general-cores

hammer

HAMMER: Highly Agile Masks Made Effortlessly from RTL

jupyter-matplotlib

Matplotlib Jupyter Extension

microcp

Tiny multipurpose USB-to-UART board

netmap

Automatically exported from code.google.com/p/netmap

peripheral-drivers

PYNQ

Python Productivity for ZYNQ

riscv-meta

RISC-V Meta – a suite of tools that operate on RISC-V ISA (Instruction Set Architecture)

rogue

SLAC Python Based Hardware Abstraction & Data Acquisition System

rogue-example

Example project for rogue

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0

testpy

ucr-eecs168-lab

The lab schedules for EECS168 at UC Riverside

verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module

vhdl-extras

Flexible VHDL library

vhdl-style