abhishek2002228

RISCV_MYTH_CORE

RISCV-MYTH Core

DRUM_Approximate_Multiplier

OSTEP_Projects

Pong_VGA

Pong game on the NexysA7-50T FPGA Board displayed using a VGA interface and written in Verilog

RISCV-Processors

Booksim_CADL

CacheSim

COMSOL_MEMS

Floating-Point-ALU

Operating-Systems-Assignments

TicTacToe_Minimax

uart-core

Basic UART RX/TX modules with FIFO interface for FPGA's

verilog-1

Repository for basic (and not so basic) Verilog blocks with high re-use potential

chisel-template-1

A template project for beginning new Chisel work

Computer_Systems_Dir

Course_Notes_3rdYear

miscellaneous

Neural-Networks-Fuzzy-Logic

Verilog

A Working Directory to keep track of my learning process in Verilog HDL