YE ZIYANG's repositories
General-Slow-DDR3-Interface
A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.
crash_analysis
Analysis for the May 7th, 2021, Shaoguan Guangdong crash.
LicheeTang20K_DDR_Test
The DDR Test Firmware for LicheeTang20K.
Verilog_TCP
Highly specialized TCP module. Simple and high-performance. No ARP support.
Downloader
Downloader by CY68013
LicheeTang25k_SDRAM
SDRAM controller for LicheeTang25k
Super-Scalar-RV32
Learn to design super scalar processors and use advanced HDLs. Design from scratch.
USB_Clock_Generator
A Clock Generator with USB Type-C, based on CH551 and MS5351 (Compatible with Si5351)
StudyInEsp32
【深度开源】wiif+bt模块esp32学习之旅（持续更新，欢迎 Star...）
chipyard_note
A personal note for head first chipyard.
Lens_Ray_Tracing
Ray tracing of convex and concave lenses
npBNN
Bayesian neural networks using Numpy and Scipy
NTT-PYTHON
A small piece of code to implement python's NTT.
palworld_game_server
palworld game server - Docker (幻兽帕鲁服务器部署脚本)
pixl.js
An emulator for Amiibo!
rathole
A lightweight and high-performance reverse proxy for NAT traversal, written in Rust. An alternative to frp and ngrok.
sipeed2022_spring_competition
sipeed2022_spring_competition
TangMega-138KPro-example
Tang Mega 138K Pro examples
TangPrimer-25K-example
TangPrimer-25K-example project
Validation
Raptor Validation - New clean version of Compiler_Validation repo
Verilog_Print
A simple Print written in verilog to help debug