Yude fang's repositories
BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
AXI-SDCard-High-Speed-Controller
A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
Language:SystemVerilogApache-2.0000
Language:Scala000
gem5-src
This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.
Language:C++BSD-3-Clause000
L2-LLC-caches
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
Language:SystemVerilogApache-2.0000
Nyuzi-GPGPU
GPGPU microprocessor architecture
Language:CApache-2.0000
opentitan
OpenTitan: Open source silicon root of trust
Language:SystemVerilogApache-2.0000
riscv-rootfs
checkpoint-fix
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sdram-controller
Verilog SDRAM memory controller
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Xuantie-C910
OpenXuantie - OpenC910 Core
Language:VerilogApache-2.0000