Yongcann

MacroPlacement

Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source

RSA-CRYPTOSYSTEM-using-verilog

RSAonVerilog

Implementation of RSA algorithm on FPGA using Verilog

encryption

Java 和 js 实现 AES 和 RSA 算法的互加解密

python-encrypt

md5，sha256哈希。aes，des，rsa，ecc加密算法

AXIMasterSlaveStream

Repo for AXIMasterStreamSlave Tutorial

corundum

Open source FPGA-based NIC and platform for in-network compute

axis_data_width_converter

dma-bench

axis_bridge_master_1.0

AXI-Streaming to AXI-MM-Master bridge

Homa-NIC

FirstX2P

This is the AXI-to-APB bridge which only supports convert AXI-32bit to APB-32 bit

robust_axi2apb

Generic AXI to APB bridge

simple-AXI2AHB-bridge

AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

robust_axi2ahb

Generic AXI to AHB bridge

linux

Linux kernel source tree

verilog-axis

Verilog AXI stream components for FPGA implementation

axis_bridge_slave_1.0

AXI-MM-Slave to AXI-Streaming bridge

FPGA-SM3-HASH

Description of Chinese SM3 Hash algorithm with Verilog HDL

wujian100_open

IC design and development should be faster，simpler and more reliable

AES-FPGA

AES加密解密算法的Verilog实现

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Kaigard.github.io

OpenNNA

一个开源的FPGA神经网络加速器。

fpga_sobel_ov5640_hdmi

fpga跑sobel识别算法

ov5640_hdmi

ZYNQ_ov5640_hdmi_frame_difference

帧差法运动目标检测，基于ZYNQ7020

CAN-Bus-Controller

An CAN bus Controller implemented in Verilog

UART

ARM中通过APB总线连接的UART模块

obd

can 总线相关