YikeZhou / systemverilog-verilog-examples-collector

SystemVerilog/Verilog Examples

This repository maintains a Python script to collect synthesizable SystemVerilog/Verilog code snippets from other repositories on GitHub. The list of source repositories lies in repos.txt.

• Prerequisites: Yosys, Synlig
• Usage: YOSYS_BINARY={path-to-yosys-executable} python3 collector.py