Jincheng Yang's repositories
projectAris
🕹️ ProjectAris aims at implementing a single core, single thread and RV32I based CPU in Verilog.
OS2023-Practices
ACM Class Operating Systems Course Practices, Year 2023
file-based-skiplist
Implementation of file-based sorted containers using skiplist
projectEureka
🚀 a Mx* compiler built with Antlr
RISCV-Simulator-2022
PPCA2022 Assignment1
TicketSystem2022
Term Project of SJTU ACM Class of 2025: Train Ticket Management System
so-vits-svc
基于vits与softvc的歌声音色转换模型
Language:PythonMIT000
testforGit
A test repository for learning Git functions.