Yuning Li's repositories
EigenVector
POSSUMM - PCA of Sparse, SUper Massive Matrices
matlab2tikz
This program converts MATLAB®/Octave figures to TikZ/pgfplots figures for smooth integration into LaTeX.
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
common_cells
Common SystemVerilog components
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
External-Attention-tensorflow
🍀 Tensorflow implementation of various Attention Mechanisms, MLP, Re-parameter, Convolution, which is helpful to further understand papers.⭐⭐⭐
FPGA-DDR-SDRAM
An AXI4-based DDR1 controller to realize mass, cheap memory for FPGA. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
FPGA-JPEG-LS-encoder
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。
FPGA-SDcard-Reader-SPI
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
FPGA-USB-Device
An FPGA-based USB full-speed device core to implement USB-serial, USB-camera, USB-audio, USB-hid, etc. It requires only 3 FPGA common IOs rather than additional chips. 基于FPGA的USB full-speed device端控制器，可实现USB串口、USB摄像头、USB音频、U盘、USB键盘等设备，只需要3个FPGA普通IO，而不需要额外的接口芯片。
github-readme-stats
:zap: Dynamically generated stats for your github readmes
HEVC-image-encoder-lite
A lightweight H.265/HEVC intra-frame encoder for grayscale image compression, with only 1600 lines of C. 一个轻量级 H.265/HEVC 帧内编码器，用于进行灰度图像压缩。代码量仅为 1600 行 C 语言，易于理解。
hwacha
Microarchitecture implementation of the decoupled vector-fetch accelerator
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
mixxx
Mixxx is Free DJ software that gives you everything you need to perform live mixes.
pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
pulp_soc
pulp_soc is the core building component of PULP based SoCs
riscv-gnu-toolchain
GNU toolchain for PULP and RISC-V
riscv-gnu-toolchain-1
GNU toolchain for RISC-V, including GCC
snitch
Lean but mean RISC-V system!
USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
wavedrom.github.io
Digital timing diagram editor
Xilinx-FPGA-PCIe-XDMA-Tutorial
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
YL29399
Config files for my GitHub profile.
zjuthesis
Zhejiang University Graduation Thesis LaTeX Template