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原博's starred repositories

NF5

A simple 5-stage Pipeline RISC-V core

Language:SystemVerilogBSD-3-Clause1600

AISystem

AISystem 主要是指AI系统，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术

Language:Jupyter NotebookApache-2.01100800

os_kernel_lab

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

Language:RustGPL-3.0396600

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

Language:TL-VerilogBSD-3-Clause22600

Tcore

Tcore是我在暑假参与清华陈渝教授带领的summer school时和同来参与研修的东南大学李可然同学决定一起做的在一个基于Rcore衍生项目，终极目标是一起做出一个基于Riscv的Cpu并且开发一个可以移植到该Cpu上完整的操作系统，将操作系统继续钻研下去

1300

Shuhai

Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4, on a Xilinx FPGA

Language:SystemVerilog9400

openpiton

The OpenPiton Platform

Language:Assembly63700

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Language:AssemblyNOASSERTION226500

ffjpeg

a simple jpeg codec.

Language:CGPL-3.010900

Cores-VeeR-EH1

VeeR EH1 core

Language:SystemVerilogApache-2.081800

keystone

Keystone Enclave (QEMU + HiFive Unleashed)

Language:CNOASSERTION46500

busybear-linux

busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.

100

vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Language:Tcl83700

NF5

A simple 5-stage Pipeline RISC-V core

BSD-3-Clause100