XDWEIUSTC / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Asynchronous dual clock FIFO

Overview

This repository stores a verilog description of dual clock FIFO. A FIFO is a convenient circuit to exchange data between two clock domains. It manages the RAM addressing internally, the clock domain crossing and informs the user of the FIFO fillness with "full" and "empty" flags.

It is widely inspired by the excellent article from Clifford Cummings, Simulation and Synthesis Techniques for Asynchronous FIFO Design <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf>_

The simulation testcases available use Icarus Verilog <http://iverilog.icarus.com>_ and SVUT <https://github.com/ThotIP/svut>_ tool to run the tests.

Documentation

• specification
• testplan