Wilson Chen's repositories
automatic-verilog
automatic-verilog based on vimscript
basic_verilog
Must-have verilog systemverilog modules
NyuziProcessor
GPGPU microprocessor architecture
ALADDIN
A pre-RTL, power-performance model for fixed-function accelerators
andes-vector-riscv-dv
Andes Vector Extension support added to riscv-dv
ara-RV-Vector-CoProcessor
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
awesome-hdl
Hardware Description Languages
Book-list-of-computational-geometry-and-computer-graphics
Book list of computational geometry and computer graphics 计算几何和计算机图形学必读书单与经典书籍
gplgpu
GPL v3 2D/3D graphics engine in verilog
hw
RTL, Cmodel, and testbench for NVDLA
kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Open_RegModel
:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
verilog-perl
Verilog parser, preprocessor, and related tools for the Verilog-Perl package