WeiChungWu

WeiChungWu

Geek Repo

Location:HsinChu, Taiwan

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WeiChungWu's repositories

vim-SystemVerilog

SystemVerilog syntax highlight/indent support in vim

Language:Vim ScriptLicense:MITStargazers:45Issues:9Issues:5

UVM_UART_Example

An UVM example of UART

Language:SystemVerilogStargazers:12Issues:1Issues:3

dotvim

my .vim setting

Language:Vim ScriptStargazers:2Issues:0Issues:0

vim-easygrep

Fast and Easy Find and Replace Across Multiple Files

Language:Vim ScriptLicense:UnlicenseStargazers:1Issues:0Issues:0