VILLASframework / fpga

In GitLab by @n-eiling on Nov 8, 2022, 16:40

Merges vc707-sg-dma -> master

also automatically configures the DMA settings from hwdef parsed json

I didn't test the polling mode, yet. But interrupts work as expected.

In GitLab by @n-eiling on Nov 8, 2022, 17:43

added 1 commit

51ed60f4 - update common submodule

Compare with previous version

In GitLab by @n-eiling on Nov 11, 2022, 09:35

mentioned in merge request acs/public/villas/node!249

Nice :) I will only do some code-style/indention fixes and afterwards we can merge it :)

I am wondering: Should be maybe move the polling setting to the InterruptController class in intc.hpp?

I think we might need to have a way for the user to provide run-time configuration on a per-IP basis like this:

fpgas = {
	vc707 = {
		# Card identification
		id = "10ee:7022"
		# slot = "88:00.0"
		
		do_reset = true

		ips = {
			@import "/global/projects/villas/fpga/software/etc/vc707-xbar-pcie/vc707-xbar-pcie.json";

			axis_interconnect_0_xbar = {
				connect = {
					"ip_a": "ip_b"
				}
			},

			dino_ch0 = {
				"sampling_rate": 10e3
			}

			axi_pcie_intc_0 = {
				polling = false
			}
		}

		// Or maybe based on VLNVs
		ips_vlnv = {
			xilinx.com:module_ref:axi_pcie_intc: = {
				polling = false
			}
		}
	}
}

A short summary of coding style changes I did:

Add spaces after casts (char *) buf instead of (char *)buf
Move braces into same line as if, for and while statements
Start comments with uppercase characters

Rebased on current master and merged

enable scatter-gather dma with interrupts - [closed]