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Move Interrupt Controller to Top Level in FPGA Design

stv0g opened this issue · comments

commented

In GitLab by @n-eiling on Nov 7, 2022, 11:46

We should move the Xilinx Interrupt Controller to the top level in the vivado design so we can parse the configuration parameters and automatically detect the real number of interrupt that the controller was configured with. This requires changing vlnv parsing.