VILLASframework / fpga

Archived: VILLASfpga has been integrated into the VILLASnode repo

https://fein-aachen.org/en/projects/villas-fpga/

Create IP class for new Aurora IP core

stv0g opened this issue 4 years ago · comments

Steffen Vogel commented 4 years ago

Example from RTDS IP core: https://git.rwth-aachen.de/acs/public/villas/fpga/blob/develop/lib/ips/rtds.cpp

Next up: define registers for Aurora Module

Status registers

Aurora link state

Control registers

Aurora Loopback

Steffen Vogel commented 4 years ago

In GitLab by @hatimak on Jun 12, 2020, 13:35

closed