Irregular reads from RTDS simulation into villas-fpga-pipe over GTFPGA
stv0g opened this issue · comments
In GitLab by @hatimak on Aug 16, 2019, 21:14
We receive the following read by villas-fpga-pipe from a simple counter running on RTDS. Most samples arrive in their sequence but there are some hiccups now and then when samples are just missing (see line 8 below).
...
1: 1;406138151;
2: 1;406138152;
3: 1;406138153;
4: 1;406138154;
5: 1;406138155;
6: 1;406138156;
7: 1;406138157;
8: 1;1;406138159;
9: 1;406138160;
10: 1;406138161;
11: 1;406138162;
12: 1;406138163;
...
For this output, the process was running on isolated cores 10-27 (18 in number) and FIFO priority 99.
We want to be able to have regular reads from the RTDS without skipping anything.
Can you try write the received data into memory rather than to stdout?
You can then dump all the memory contents to stdout after the program stops..
In GitLab by @n-eiling on Nov 29, 2022, 14:57
we don't use the gtfpga interface anymore
Yes lets close it. I also think this might be resolved by the new/fixed IRQ support.