VILLASframework / fpga-hardware

VILLASframework/fpga-hardware Issues

Make project REUSE compliant
Updated a year ago
Reduce size of PCIE BAR0 to 1M to avoid mapping issues when detecting the PCIe device post-bootup
Updated 4 years ago
Create overview table over different Aurora IP parameters for RTDS, OPAL-RT & FPGA partners
Updated 4 years ago
Xilinx-Ubuntu VM unreachable
Closed 2 years ago1
Add constraints for faster technologies SFP/FMC module
Closed 2 years ago2
Complete location constraints for Trenz FMC/SFP module
Closed 2 years ago2
Testing Aurora IP core with ZCU106 board
Updated 4 years ago
Dev - [closed]
Closed 2 years ago1
Add AXI EMC controller to VC707 design for flashing bitstream into configuration memory via PCIe
Updated 4 years ago4
Irregular reads from DMA
Updated 2 years ago2
WIP: Add tlast and tready signals to aurora_axis - [closed]
Closed 2 years ago1
WIP: New Makefile - [closed]
Closed 2 years ago11
Implement AXI_S_WSTRB logic
Closed 2 years ago2
Add intra-frame delay timer and respective status register
Updated 4 years ago
Upgrade hw_server on Ernie to Vivado 2019.1
Closed 2 years ago1
Move aurora-rtds project into `ips` folder
Closed 2 years ago2
Add Verilog code to aurora-rtds IP to generate sequence numberes
Closed 2 years ago4
Include IP core version into IP TCL scripts and emit warning if version mismatch
Updated 5 years ago
Licensing issue with Vivado 2019.1
Closed 2 years ago3