Thomasb81

Midi_SynthFpga

Sound synthetizer with an fpga

adaptagrams

Libraries for constraint-based layout and connector routing for diagrams.

hdlConvertor

verilog and vhdl parser module for python

adaptagram2

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

cocotbext-ahb

Cocotb AHB Extension - AHB VIP

dunnart

Constraint-based diagram editor

elkjs-svg

grammars-v4

Grammars written for ANTLR v4; expectation that the grammars are free of actions.

jinja

A very fast and expressive template engine.

myhdl

The MyHDL development repository

nanobind

nanobind — Seamless operability between C++17 and Python

planarity

Planar graph algorithms

SD_spi

SPI / SDCard through serial controler experiment

SDCard-PG

SD Card play ground

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

simpleparse

SimpleParse parser generator using mxTextTools (launchpad mirror)

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

verilog-arbiter

A look ahead, round-robing parametrized arbiter written in Verilog.

WeasyPrint

The awesome document factory

ZIA

ZIA Code Repository

ZPUino-HDL

ZPUino HDL implementation