Tang-Haojin / YuQuan

A RISC-V core running Debian.

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YuQuan Project

Contents at a glance:

  • .gitignore - helps Git ignore junk like generated files, build products, and temporary files.
  • build.sc - instructs mill to build the Chisel project
  • Makefile - rules to call mill
  • playground/src - source directory
  • playground/src/Elaborate.scala - wrapper file to call chisel command with the target module
  • playground/test/src - tester directory
  • playground/sim/src - simulation directory
  • playground/sim/Elaborate.scala - wrapper file to call chisel command with the simulation module

Getting Started

First, install mill by referring to the documentation here.

To run all tests in this design (recommended for test-driven development):

make test

To generate Verilog:

make verilog

To run simple test:

make sim

To load program from bin and run test, copy $BIN-$ISA-nemu.bin to playground/sim/bin/, and run:

make BIN=$BIN [ISA=$ISA] sim

If ISA is not specified, it defaults to riscv64.

To disable difftest, run:

make BIN=$BIN DIFF=0 sim

About

A RISC-V core running Debian.


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Language:Scala 74.3%Language:Verilog 12.6%Language:C++ 10.0%Language:Makefile 1.5%Language:SystemVerilog 1.3%Language:Python 0.2%Language:Shell 0.1%