SuperWWF

AMBA_AXI3

System Verilog and Emulation. Written all the five channels.

axi-bfm

AXI3 Bus Functional Models (Master & Slave)

AXI3_VIP

Xillinx AXI Verification IP VLNV:axi_vip1.1@Vivado 2017.4

2019_20

Computational-Neuroscience

Some coursework

computational-neuroscience-1

Implementation-of-AMBA-AXI3-protocol

Design and verify the AMBA AXI protocol with single master-slave from scratch in System Verilog. Debugging the design using both a System Verilog simulator and the Mentor Graphics Veloce hardware emulator.

learnsystemc

Learn systemC with examples

matplotlib-tutorial

Matplotlib tutorial for beginner

Python_Code

Some useful python script

pytorch-semseg

Semantic Segmentation Architectures Implemented in PyTorch

RISCV_TRY

SDN_Project

Based on NetFPGA project

Search_Excel

Stencil

HPC Coursework

tutorials

机器学习相关教程

Web_Learn

Web_Learn

zhiyuli.github.io

Learning